`timescale 1ns / 1ps
include "defines.v";
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:47:47 12/29/2020 
// Design Name: 
// Module Name:    DM_Extender 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module DM_Extender(
    input isSigned,
    input [1:0] type,
    input [31:0] memData,
    output reg [31:0] outData
    );
	always @*
	begin
		case (type)
			`WORD:
			begin
				outData = memData;
			end
			`HALFWORD:
			begin
				if(isSigned)
					outData = {{16{memData[15]}},memData[15:0]};
				else outData = {{16'd0},memData[15:0]};
			end
			`BYTE:
			begin
				if(isSigned)
					outData = {{24{memData[7]}},memData[7:0]};
				else outData = {{24'd0},memData[7:0]};
			end	
		endcase
	end

endmodule
